Embedded System Engineer (m/f)

Description des tâches:


Position Summary

We are seeking a Senior Embedded Systems Engineer to support the design, development, and integration of our next-generation space payloads. Our systems focus on Space Domain Awareness (SDA), Space Situational Awareness (SSA), and autonomous Rendezvous and Proximity Operations (RPO).
Working alongside established Flight Software (FSW), Systems, and Computer Vision (CV) teams, you will bridge the gap between payload concept and physical execution—translating sensor and processing requirements into robust, high-performance embedded hardware, FPGA pipelines, and firmware architectures deployable at the edge in orbit.


Key Responsibilities:

• Support the end-to-end architecture, design, and selection of embedded hardware and processing platforms (ARM, RISC-V, FPGAs, GPUs/NPUs) powering advanced optical/SDA payloads.
• Perform architectural trade-off studies, component evaluation, and environmental/radiation tolerance assessments for space-bound hardware.
• Evaluate, integrate, and deploy edge-compute hardware platforms, SoC FPGAs, and development kits—including AMD/Xilinx Zynq MPSoCs, Microchip PolarFire / RT PolarFire SoCs, space-grade compute modules, and AI accelerators (e.g., Hailo)—to support flight software and computer vision workloads.
• Collaborate with Flight Software and Computer Vision teams to define clear HW/SW partitioning for computationally heavy edge tasks.
• Implement custom FPGA logic and firmware for high-speed sensor interfaces, deterministic data pipelines, and on-orbit hardware-accelerated processing.
• Integrate image sensors, radios, and power electronics using robust low- and high-speed interfaces (e.g., I²C, SPI, UART, CAN, SpaceWire, LVDS, MIPI-CSI, PCIe, Ethernet).
• Develop embedded avionics solutions supporting spacecraft command, control, and payload data management.
• Support verification and validation (V&V) campaigns, environmental/HIL (Hardware-in-the-Loop) testing, and prepare standard technical and engineering documentation.


Experience & Qualifications:

• Background: Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, Aerospace Engineering, or a related technical field.
• Work Experience: 3–5+ years of professional experience in embedded systems hardware design, FPGA development, or low-level embedded engineering.
• Cross-Functional Collaboration: Eagerness and ability to work at the intersection of complex domains, specifically Computer Vision and Flight Software teams.
• Communication: Excellent English proficiency with the ability to write and manage standard documentation, software documentation, and scientific documentation.
• Autonomy: Strong ability to work autonomously under own initiative and without direct supervision
• Technical:
o Practical experience with FPGA development (VHDL, Verilog, or SystemVerilog) and industry toolchains (e.g., Microchip Libero SoC for PolarFire, Xilinx/AMD Vivado, or Intel/Quartus).
o Solid proficiency in C/C++ for embedded microcontrollers (e.g., STM32 / ARM Cortex-M) and real-time operating systems (FreeRTOS).
o Working knowledge of ARM and RISC-V architectures (e.g., Zynq ARM Cortex cores, PolarFire RISC-V MSS), high-performance compute modules, and FPGA/SoC integration.
o Hands-on experience with PCB bring-up, debugging physical interfaces, and test instrumentation.
o Working proficiency in Python, C++ working proficiency
• Nationality: EU nationality is mandatory due to project requirements.


Assets (Nice to have):

• Space/Aerospace Experience: Prior experience with space payload hardware, satellite avionics, radiation-tolerant design, or ECSS standards.
• Embedded Linux: Experience creating custom OS images using Yocto Linux for embedded gateways or edge processing platforms.
• Hardware-in-the-Loop (HIL) & V&V: Experience designing or executing structured Verification & Validation (V&V) testbenches for embedded hardware.
• Edge-AI & Acceleration: Familiarity with edge AI deployment, model quantization, or hardware acceleration of Deep Learning algorithms on FPGAs/NPUs.
• Hardware-AI deployment toolchains: Familiarity with hardware-AI deployment toolchains (e.g., AMD Vitis AI, Hailo Dataflow Compiler) and integrating heterogeneous architectures (ARM + FPGA + NPU/AI Accelerator)
• Containerization: Experience with Docker for standardized build environments and toolchain deployment.